1. Technical Field
The present invention generally relates to a semiconductor apparatus, and more particularly, to a nonvolatile memory apparatus, an operating method thereof, and a data processing system having is the same.
2. Related Art
A nonvolatile memory apparatus may include a flash memory, a phase change RAM (PCRAM), a resistive RAM (ReRAM), a magnetic RAM (MRAM) and the like. In particular, the PCRAM or MRAM is a nonvolatile memory apparatus which writes and senses data according to a current driving method.
During a program operation for a nonvolatile memory cell, a program and verify (PNV) operation is performed to accurately write data.
Particularly, in the nonvolatile memory apparatus based on the current driving method, a resistance distribution of each cell may deviate from a desired range after a program operation, due to various factors existing on a program path and a non-uniform resistance distribution of each cell. When the resistance distribution deviates from the desired range, a sensing margin may be degraded. In this case, it is impossible to guarantee the reliability of read data. Therefore, the program operation of the nonvolatile memory apparatus accompanies a verify process through which the resistance distribution of each cell is adjusted within the desired range.
In general, a PNV (program and verify) pulse (a) is enabled during one period of a data write operation, and a program pulse (b) is enabled to write data into a cell during a part of the PNV period. Furthermore, after the program pulse (b) is disabled, a verify and compare pulse (c) is enabled to check whether accurate data was written into the cell or not, thereby determining whether an additional program operation is required or not.
The nonvolatile memory apparatus has developed from a single-level cell (SLC) method to a multi-level cell (MLC) method. Regardless of whether the nonvolatile memory apparatus is implemented based on the SLC method or the MLC method, a PNV process for each data level is performed according to a predetermined timing.
Referring to FIG. 2, (a) represents a pulse which is enabled while all data are programmed into a memory cell array (t101 to t108), for example, a write enable pulse WE. Here, t101 to t108 may be timing periods. Further, (b1), (b2), and (b3) represent PNV pulses when data having a relatively long program time (for example, first data) are written, and (c1), (c2), and (c3) represent PNV pulses when data having a relatively short program time (for example, second data) are written.
Referring to (b1) and (c1), PNV pulses for writing first and second data is enabled at the same time as the pulse (a) is enabled at the time point t101. In this case, since a PNV time for the second data is relatively short, the PNV pulse for the second data is disabled at the time point t102, but the PNV pulse for the first data is disabled at the time point t103.
Therefore, during a time Δt1 required until the PNV pulse for the first data is disabled after the PNV pulse for the second data is disabled, devices to perform a program operation for the second data is are in a waiting state.
Referring to (b2) and (c2), a PNV pulse for the first data is enabled to perform a PNV operation at the time point t101. At this time, a PNV pulse for the second data is disabled. After the PNV pulse for the first data is disabled at the time point t103, the PNV pulse for the second data is enabled to perform a PNV operation for the second data from the time point t104 to the time point t105. Then, the PNV pulse for the first data is enabled again at the time point t106.
In this case, while the PNV operation for the first data is performed (Δt2), devices to perform the PNV operation for the second data are in a waiting state, and while the PNV operation for the second data is performed (Δt3), devices to perform the PNV operation for the first data are in a waiting state.
Referring to (b3) and (c3), after a PNV operation for the first data is completed (t101˜t107), a PNV operation for the second data is performed (t107˜t108). Therefore, during a time Δt4, the devices to perform the PNV operation for the second data are in a waiting state, and during a time Δt5, the devices to perform the PNV operation for the first data are in a waiting state.
In this PNV method, after the program operations for all data are completed, the verify operations are performed at a time or the data are reprogrammed (b1 and c1). The PNV operation is alternately performed for the respective data levels (b2 and c2). Alternatively, after a PNV operation for any one data level is completed, a PNV operation for another data level is performed (b3 and c3).
Therefore, when data having a short program time is programmed and verified, the next PNV operation is performed after a program operation for data having a long program time is ended. Therefore, a long time is required for the program operation. In order to accurately write data, the number of PNV operations is inevitably increased. As the number of PNV operations is increased, the waiting time is accumulated to increase the entire PNV time. Accordingly, the performance of the entire system may be degraded.